1. Field of the Invention
The present invention relates to a microcomputer and, more particularly, to a microcomputer internally provided with an oscillator circuit, wherein the driving ability of the oscillator circuit can be changed.
2. Description of Related Art
in a single-chip microcomputer internally provided with an oscillator circuit, the driving ability of the oscillator circuit can be changed by rewriting the content of a register under the control of a CPU, so as to reduce power consumption and an unnecessary emission by oscillation.
FIG. 1 is a block diagram showing the constitution of a conventional microcomputer of this type. Together with a ceramic-resonator or a crystal oscillator, a capacitor for oscillation and the like are connected to the microcomputer. The microcomputer comprises a clock input terminal 1 to which a clock is to be inputted and a clock output terminal 2 from which the clock is to be outputted. The clock input terminal 1 is connected to one input terminal of each of NAND circuits 3 and 4.
An interrupt request signal (hereinafter referred to as an interrupt signal) INT is inputted to one input terminal of an OR circuit 18, while a reset signal RST is inputted to the other input terminal thereof. The output terminal of the OR circuit 18 is connected to the set terminal S of an RS flip-flop 9. To the reset terminal R of the RS flip-flop 9 inputted is an oscillation stop signal STP, while the output terminal Q of the flip-flop 9 is connected to the other input terminal of each of the NAND circuits 3 and 4. The output terminal Q of the flip-flop 9 is connected to the other input terminals of the NAND circuits 3 and 4. The output terminal of the NAND circuit 4 is connected via a switch 11 to the input side of a frequency divider 5 for dividing the frequencies of the clocks from the NAND circuits 3 and 4. The output terminal of the NAND circuit 4 is also connected to the clock output terminal 2, to the output terminal of the NAND circuit 3, and to one input terminal of an AND circuit 10.
The output side of the frequency divider 5 is connected to the input side of a selector 6 for selecting a divided frequency clock from the frequency divider 5. The output side of the selector 6 is connected to the input side of a counter 7, which also serves as a watch dog timer. The output side of the counter 7 is connected to one input terminal of an OR circuit 12. To the other input terminal of the OR circuit 12 inputted is a reset signal RST. The output terminal of the OR circuit 12 is connected to the set terminal S of an RS flip-flop 8. To the reset terminal R of the flip-flop 8 inputted is the oscillation stop signal STP.
The output terminal Q of the flip-flop 8 is connected to the other input terminal of the AND circuit 10 and to one input terminal of an OR circuit 14 via an inverter 16. The AND circuit 10 outputs an internal clock i to be given to the CPU (not shown) and the like. To the other input terminal of the OR circuit 14 inputted is the content of a select bit 20 composed of a register in which an instruction to select the divided frequency clock from the frequency divider 5 is written. The output from the OR circuit 14 is given to the selector 6. A select bit 21 is composed of a register for controlling the driving ability of the oscillator circuit by turning the switch 11 on and off. The content s of the select bit 21 is given to the switch 11. The NAND circuits 3 and 4 and switch 11 constitute an oscillator circuit part 50.
FIG. 2 is a block diagram showing specific constitutions of the frequency divider 5, selector 6, and counter 7 of FIG. 1. The frequency divider 5 consists of half frequency divider circuits 101, 102, 103 . . . 105 . . . 109 for halving the frequency of the clock inputted from the clock output terminal 2, which are connected in series. From the half frequency divider circuits 101, 102, 103 . . . 105 . . . 109 are outputted clocks f.sub.2, f.sub.4, f.sub.8 . . . f.sub.32 . . . f.sub.512 with halved frequencies.
The selector 6 consists of: transfer gates 161 and 162 the output sides of which are connected in common; a buffer 163 the input side of which is connected to the output sides of the transfer gates 161 and 162; and an inverter 164 the input side of which is connected to the gate of an N-channel transistor of the transfer gate 161 and to the gate of a P-channel transistor of the transfer gate 162 and the output side of which is connected to the gate of a P-channel transistor of the transfer gate 161 and to the gate of an N-channel transistor of the transfer gate 162. The input side of the transfer gate 161 (162) is connected to the output side of the half frequency divider circuit 105 (109). The gate of the N-chan/el transistor of the transfer gate 161 and the gate of the P-channel transistor gate of the transfer gate 162 are connected to the output terminal of the OR circuit 14.
The counter 7 consists of: half frequency divider circuits 201, 202 . . . 211, 212, which are connected in series and each of which constitutes a counter that increments itself; and a reset control circuit 170 for resetting the half frequency divider circuits 201, 202 . . . 211, 212. The input side of the half frequency divider circuit 201 is connected to the output side of the buffer 163. If the counted value reaches a specified value, a signal h (g) is outputted from the half frequency divider circuit 202 (211). An overflow signal f outputted from the half frequency divider circuit 212 is inputted to the reset control circuit 170. To the reset control circuit 170 inputted are a reset signal RST, an oscillation stop signal STP, and a write signal WRT.
FIG. 3 is a block diagram showing a specific constitution of the oscillator circuit part 50. One input terminal of a NAND circuit 57, to which the output p from the flip-flop 9 is inputted, is connected to the gate of a transistor 41 interposed between a power source V.sub.D and the clock output terminal 2, to the input side of an inverter 59, and to the gate of a transistor 56. The output side of the inverter 59 is connected to the gate of a transistor 53. The output side of an inverter 49, to which a signal s from the select bit 21 and a signal sa from an AND circuit 13 are inputted, is connected to the other input terminal of the NAND circuit 57. The output terminal of the NAND circuit 57 is connected to the gate of a transistor 52 and to the input side of an inverter 58. The output side of the inverter 58 is connected to the gate of a transistor 55.
A series circuit consisting of the transistors 52 and 55 and a series circuit consisting of the transistors 53 and 56 are connected in parallel. The source sides of the transistors 52 and 53 are connected to the power source V.sub.D via a transistor 51. The drain sides of the transistors 55 and 56 are connected to the ground via a transistor 54. The joint between the transistors 52 and 55 and the joint between the transistors 53 and 56 are connected in common to the joint between a transistor 41 and the clock output terminal 2. The gates of the transistors 51 and 54 are connected in common to the clock input terminal 1.
FIG. 4 is a block diagram showing the single-chip microcomputer to which an external oscillator and the like are connected. Between the clock input terminal 1 and clock output terminal 2 provided in a microcomputer 310 mounted is a parallel circuit consisting of a resistance 312 and, e.g., a ceramic resonator 311. The clock input terminal 1 and clock output terminal 2 are grounded via capacitors 313 and 314, respectively.
FIG. 5 is a block diagram showing a specific constitution of the select bits 20 and 21. A data bus 65 is connected to the input terminal D of a D flip-flop 71, the output terminal Q of which is connected to the data bus 65 via an output buffer 75. The content s written in the select bits 20 and 21 is outputted from the output terminal Q of the flip-flop 71. An address bus 66 is connected to the input side of an address decoder 73, the output side of which is connected to one input terminal of each of AND circuits 74 and 76. The output terminal of the AND circuit 74 is connected to the clock terminal CK of the flip-flop 71. A write signal line 67 is connected to the other input terminal of the AND circuit 74. A read signal line 68 is connected to the other input terminal of the AND circuit 76, the output terminal of which is connected to the output control terminal of the buffer 75. A reset signal line 69 is connected to the reset terminal RS of the flip-flop 71.
Next, the operation of the microcomputer will be described with reference to FIG. 6 showing a timing chart of signals to individual parts. In a state in which a specified source voltage is supplied to the microcomputer 310 and the reset signal RST at the L level is inputted thereto, each of the flip-flops 8 and 9 is in the set state, so that the outputs p and a from the flip-flops 8 and 9 are at the H level. The select bits 20 and 21 are reset, as shown in FIGS. 6(E) and 6(H), so that the counter 7 is reset. In a state in which the select bit 21 is reset, the switch 11 is on and therefore the output p from the flip-flop 9 is at the H level. As a result, each of the NAND circuits 3 and 4 is brought into the active state and inverts the clock from the clock input terminal 1, so that the inverted clock is outputted to the clock output terminal 2.
Since the ceramic resonator 311, capacitors 313 and 314, and the like are connected between the clock input terminal 1 and clock output terminal 2, as shown in FIG. 4, oscillating operation is performed so that the clock shown in FIG. 6(B), which is composed of sinusoidal voltages having opposite phases, can be obtained at each of the clock input terminal 1 and clock output terminal 2. The cycle, i.e., oscillating frequency of the clock is determined by the oscillating characteristic of the ceramic resonator 311. The clock thus generated is inputted to the frequency divider 5. After the initiation of the oscillating operation, the frequency divider 5 continues to divide the frequency of the inputted clock one after another by means of the half frequency divider circuits 101, 102, 103 . . . 105.
Here, if it is assumed that the frequency of the clock at the clock output terminal 2 is f.sub.out, the frequency f.sub.2 of a divided frequency clock outputted from the half frequency divider circuit 101 is f.sub.out /2, and the frequency f.sub.8 of the divided frequency clock outputted from a half divider circuit 103 becomes f.sub.out /8. Since the output a from the flip-flop 8 is at the H level and the select bit 20 is at the L level, as shown in FIG. 6(C), the transfer gate 162 of the selector 6 is turned on, while the transfer gate 161 of the selector 6 is turned off, so that a divided frequency clock f.sub.512 outputted from the half divider circuit 109 is selected, as shown in FIG. 6(G). The divided frequency clock f.sub.512 selected is inputted to the counter 7 via the buffer 163.
In the reset state, the counter 7 is always reset to "0" (000.sub.16). If the reset signal is switched to the H level at a time t.sub.0 for reset cancellation, the counter 7 initiates the counting of the divided frequency clock f.sub.512. The counter 7 is used as a supervisory timer (watch dog timer) for detecting the run away of the CPU and outputting an interrupt signal, except for the period during which oscillation is stable, i.e., the period during which the oscillating operation, which will be described later, is at a halt and except for the period from the initiation of the oscillating operation to the initiation of the supply of the internal clock.
Since the output a from the flip-flop 8 is at the H level, the AND circuit 10 is brought into the active state and supplies the clock, outputted to the clock output terminal 2, to a specified circuit such as the CPU (not shown) as an internal clock i. The microprocessor can be arranged so that a divided frequency clock x, having the same frequency as that of the divided frequency clock f.sub.2 outputted from the half frequency divider circuit 101 of FIG. 2, is inputted to the AND circuit 10, instead of the clock from the clock output terminal 2.
After reset cancellation, the CPU in the microcomputer 301 is activated by the internal clock i so as to execute a specified program. The counter 7 counts up from the initial value 000.sub.16, as described above, and if the counted value reaches a specified value and causes an over flow, it outputs the over flow signal f. In the case where the counter 7 is used as a supervisory timer for the CPU, a non-maskable interrupt is caused by the over flow signal f, so that the counter 7 is reset by the program, before the over flow of the counted value occurs, so as to prevent the above non-maskable interrupt, thus returning the counted value to the initial value 000.sub.16.
The counter 7 is reset by the reset control circuit 170 in response to the reset signal RST, write signal WRT to the counter 7, oscillation stop signal STP according to an oscillation stop instruction which will be described later, and over flow signal f. The select bit 20 is for selecting either of the divided frequency clocks f.sub.32 and f.sub.512 to be counted by the counter 7. If the divided frequency clock f.sub.512 was selected after resetting, the divided frequency clock f.sub.32 is selected by writing "1" in the select bit 20. After the activation of the CPU, the internal clock with a frequency appropriate for the operation of the CPU is selected to be supplied to the CPU.
Under such conditions, the switch 11 is on and the NAND circuits 3 and 4 combine to function as an oscillator circuit. The driving ability of the oscillator is large, because it equals to the combined outputs from the NAND circuits 3 and 4.
After supplying the power source voltage, to reduce the time period from the initiation of the oscillating operation to the stabilization of oscillation, it is necessary to increase the driving ability as described above. If the driving ability is large, however, the current consumed in the NAND circuits 3 and 4 is increased.
Since the physical circuit of the oscillator circuit part 50 is as shown in FIG. 3, the output p from the flip-flop 9 is at the L level in each oscillation stopped state, while the P-channel transistors 52 and 53 and N-channel transistors 55 and 56 are turned off and the P-channel transistor 41 is turned on. Consequently, the clock output terminal 2 shifts to the H level, thereby realizing such a state as if the NAND circuits 3 and 4 of FIG. 1 actually existed.
Once the oscillating operation is stabilized, the driving ability can be reduced. Since a smaller driving ability consumes less current, the driving ability of the oscillator circuit is switched by turning the switch 11 off. In switching the driving ability, the CPU activated by the internal clock i writes "1" in the select bit 21, with the result that the content s of the select bit 21 shifts to the H level, thereby turning the switch 11 off. The driving ability of the oscillator circuit, which depends solely on the NAND circuit 3 in this state, becomes small accordingly. After turning on the power, in consideration of the fact that the reset signal RST is not generated, the CPU writes "0" in the select bit 21 before the oscillation stop signal STP is outputted so that the select bit 21 is brought into the reset state when the power is on (in all ordinary applied system, the select bit 21 is reset by an external IC for resetting immediately after turning on the power).
The program executed by the CPU contains the oscillation stop instruction for stopping the oscillating operation of the oscillator circuit. Below, a description will be given to the operation of the microcomputer when the oscillation stop instruction is to be executed. After writing "0" in the select bit 21, as shown in FIG. 6(H), if the oscillation stop signal STP serving as the oscillation stop instruction is generated at a time t.sub.1, each of the flip-flops 9 and 8 is reset, so that the output p shifts to the L level as shown in FIG. 6(C), while the output a shifts to the L level. When the output p shifts to the L level, the outputs from the NAND circuits 3 and 4 are fixed to the H level, thus stopping the oscillating operation, as shown in FIG. 6(B). When the output a shifts to the L level, as shown in FIG. 6(C), the output from the AND circuit 10 is fixed to the L level, so that the internal clock i is halted at the L level as shown in FIG. 6(D), thus stopping the supply of the internal clock i. On the other hand, the counter 7 is reset.
To return from the oscillation stopped state subsequently, the reset signal or interrupt signal can be used. Since the description has already given to the case where the reset signal RST is used, a description will be given to the case where the interrupt signal INT is used to achieve a return from the oscillation stopped state. In the oscillation stopped state, if an input terminal for the interrupt signal (not shown) is switched to the L level at a time t.sub.2, the interrupt signal INT at the H level is generated. As a result, the output from the OR circuit 18 shifts to the H level, which in turn sets the flip-flop 9, so that the output p from the flip-flop 9 shifts to the H level. The NAND circuits 3 and 4 are thereby brought into the active state, so that the oscillator circuit part 50 resumes the oscillating operation. As described above, since "0" has been written in the select bit 21 prior to the outputting of the oscillation stop signal STP, the switch 11 is turned on as well as the NAND circuit 4 functions effectively, so that the driving ability of the oscillator circuit becomes large.
As shown in FIG. 6(B), the flip-flop 8 has been in the same state since it was reset by the oscillation stop signal STP, which stopped the oscillating operation, and its output a remains at the L level. The output from the OR circuit 14 is thereby switched to the H level and the selector selects the frequency divided clock f.sub.32, so that the supply of the internal clock i, which is fixed to the L level, is stopped. In this state, the frequency of the clock from the clock output terminal 2 is divided by the frequency divider 5 and the divided frequency clock f.sub.32, which has been selected by the selector 6, is inputted to the counter 7, so as to be counted. The counter 7 then initiates the counting from the initial value 000.sub.16.
It is assumed that the oscillating frequency of the clock to be counted is represented by f.sub.(XIN). If the frequency of the clock is f.sub.(XIN) at the time when oscillation is initiated, the counter 7 outputs the over flow signal f at the H level at a time t.sub.3 after 1/f.sub.(XIN) .times.32.times.2048 seconds elapsed, as shown in FIG. 6(F). The over flow signal f sets the flip-flop 8 so that its output a shifts to the H level, which brings the AND circuit 10 into the active state, thus initiating the supply of the internal clock i from the time t.sub.3, as shown in FIG. 6(D).
On the other hand, the output from the inverter 16 shifts to the L level, while the selector 6 is controlled only by the content of the select bit 20. Thus, by measuring the time period from the initiation of the oscillating operation to the initiation of the supply of the internal clock i by means of the counter 7, the voltage level immediately after initiating oscillation and the clock with an unstable oscillating frequency are not supplied as the internal clock i to a specified circuit, such as the CPU. If "1" is not written in the select bit 20, a signal at the L level is given from the OR circuit 14 to the selector 6, so that the selector 6 is switched to select the divided frequency clock f.sub.512, which is lower in frequency than the divided frequency clock f.sub.32.
If "1" is written in the select bit 21 at a time t.sub.4 by the CPU which is operated by the internal clock i supplied thereto, for example, the content s of the select bit 21 shifts to the H level, as shown in FIG. 6(H), and the switch 11 is turned off, so that the driving ability of the oscillator circuit becomes small. If "1" is written in the select bit 20 at a time t.sub.5 by the CPU, the content of the select bit 20 shifts to the H level, as shown in FIG. 6(E), which is then given to the selector 6, so that the divided frequency clock f.sub.32 is selected as shown in FIG. 6(G). Accordingly, the internal clock i with a different frequency is properly selected for operating the CPU.
If "0" is written in the select bit 21 (reset) at a time t.sub.6, on the other hand, the switch 11 is turned on and the driving ability of the oscillator circuit becomes large, as shown in FIG. 6(I). The changes at times t.sub.8, t.sub.9, and t.sub.10 after the generation of the oscillation stop signal STP at t.sub.7 become similar to the changes at the times t.sub.2, t.sub.3, and t.sub.4. If "1" is written in the select bit 21 at a time t.sub.10, the switch 11 is turned off and the driving ability of the oscillator circuit becomes small, as shown in FIG. 6(I). In the case where the driving ability is small, as described above, if the oscillation stop signal STP is generated at a time t.sub.12 so as to stop the oscillating operation and then the interrupt signal INT is generated at a time t.sub.13, it follows that the oscillating operation is initiated with the driving ability being small, so that it requires a long period of time for oscillation to be stabilized. In some cases, an oscillation does not occur at all.
Next, a description will be given to the operation of writing data in select bits 20 and 21 with reference to FIGS. 5 and 7. If the CPU decodes an instruction to write data in the select bit 21, it outputs the address A.sub.i of the select bit 21 shown in FIG. 7(B) to the address bus 66, data D1.sub.i shown in FIG. 7(C) to the data bus 65, and a write signal WR. Then, the address decoder 73 decodes the address A.sub.i and switches the output A from the address decoder 73 to the H level, as shown in FIG. 7(E). The AND circuit 74 carries out the logical product between the output A and the write signal WR and outputs a write signal W to the clock terminal CK of the flip-flop 71, as shown in FIG. 7(F). In response to the write signal W, the flip-flop 71 latches the data on the data bus 65. At the fall of the write signal W, the output level of the flip-flop 71 is changed so as to write "1" or "0" in the select bit 21, in accordance with the content s.
Thus, in the conventional microcomputer, it is necessary to write "0" in the select bit 21 prior to the generation of the oscillation stop signal STP, which is for reducing the current consumed in the oscillator circuit, and to write "1" in the select bit 21 after the supply of the internal clock i, which enabled a return from the state in which the oscillating operation is stopped, so as to provide a large driving ability in initializing the oscillating operation and a small driving ability after oscillation was stabilized and the internal clock was supplied. Therefore, not only the program is intricate due to the necessity for the CPU to give a write instruction, but also oscillation may not be obtained if an error arises in writing in the program such a write instruction. If the oscillating operation is initiated with a small driving ability by mistake, it disadvantageously requires a long period of time for oscillation to be stabilized. In the worst case, an oscillation may not occur at all.
In the case where the oscillating operation is performed with the driving ability being small in a product test on a microcomputer, there is a possibility that an oscillation does not occur when the user uses the microcomputer. This also brings about a problem that a defective product is not detected in the product test, so that there is a possibility that microcomputers which exhibit unstable oscillating operations appear on the consumers, market. Even when an external clock in stable oscillation is inputted to the clock input terminal without using an oscillator, in order to achieve a return from the oscillation stopped state, the internal clock cannot be supplied until the over flow signal is outputted from the counter. Consequently, even when a stable external clock is inputted, a long period of time is required to initiate the supply of the internal clock. Moreover, there is a possibility that the content of the select bit suffers an unexpected change due to a bug in the program, an alien noise, or the like.